Hardware SecurityResearch
Project Lavalamp
FPGA Hardware Security · CPU Side-Channel Mitigation
An FPGA-based hardware security device that neutralizes a class of CPU timing side-channel attacks on modern multi-threaded CPUs — the kind of attacks where a co-resident process can extract cryptographic key material by observing micro-architectural timing signals. Lavalamp ships as transparent hardware: no application changes, no OS patches, no performance regression. Brought to market after every major CPU vendor declined to deliver a microcode-level fix.
At a Glance
Order-of-magnitude reduction in side-channel leakage versus an unmitigated baseline
Negligible CPU overhead in the production FPGA path — measured as a fraction of a percent
OS-transparent: zero application changes, zero kernel patches, no recompilation required
Covers public cloud (AWS / Azure / GCP), browser workloads (WASM), VDI, exchanges, and post-quantum primitives (ML-KEM / Kyber)
Hardware-rooted entropy pipeline — proprietary masking stack details held under NDA
Vendor-independent: works regardless of upstream CPU microcode decisions
Three product tiers — Lavalamp Lite (USB FPGA), Lavalamp Pro (PCIe), Lavalamp OEM (IP-core licensing)
Independent third-party benchmark engagement underway; full numbers released only under evaluation NDA
Signal Before & After Mitigation
Let's Talk
Interested in Lavalamp?
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